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25AA320/25LC320/25C320
3.5
Read Status Register Instruction
The Write Enable Latch (WEL) bit indicates the status
( RDSR )
The Read Status Register instruction ( RDSR ) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
of the write enable latch. When set to a ‘ 1 ’, the latch
allows writes to the array, when set to a ‘ 0 ’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the STA-
TUS register. This bit is read-only.
7
WPEN
6
X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
WIP
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
The Write-In-Process (WIP) bit indicates whether the
25XX320 is busy with a write operation. When set to a
‘ 1 ’, a write is in progress; when set to a ‘ 0 ’, no write is
in progress. This bit is read-only.
bits are nonvolatile.
See Figure 3-6 for the RDSR timing sequence.
FIGURE 3-6:
CS
READ STATUS REGISTER TIMING SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
0
1
High-Impedance
Data from STATUS Register
SO
7
6
5
4
3
2
1
0
DS21227F-page 10
? 2008 Microchip Technology Inc.
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